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  product specification ps011706-0511 z80c30/z85c30 cmos scc serial communications controller copyright ?2011 zilog ? , inc. all rights reserved. www.zilog.com
ps011706-0511 cmos scc serial communications controller product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) are intended for surgical impl ant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2011 zilog, inc. all rights reserved . information in this publication co ncerning the devices, applications, or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. z8 is a registered trademark of zilog, inc. all othe r product or service names are the property of their respective owners. warning:
ps011706-0511 revision history cmos scc serial communications controller product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no may ? 2011 06 corrected ordering information section to reflect lead-free parts; updated logo and style to conform to current template. 72 , all jun ? 2008 05 updated zilog logo, zilog text, dis claimer as per latest template. all sep ? 2004 01 original issue all
ps011706-0511 table of contents cmos scc serial communications controller product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 other features for z85c30 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ctsa, ctsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dcda, dcdb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dtr/reqa, dtr/reqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 iei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ieo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 intack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 rxda, rxdb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 rtxca, rtxcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 rtsa, rtsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 synca, syncb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 txda, txdb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 trxca, trxcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 w/reqa, w/reqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 z85c30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 a/b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 d7?d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 d/c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 z80c30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ad7?ad0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 cs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 cs1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ps011706-0511 table of contents cmos scc serial communications controller product specification v ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 i/o interface capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 cpu/dma block transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scc data communications ca pabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 asynchronous modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 synchronous modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 digital phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 auto echo and local loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 sdlc fifo frame status fifo enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 z85c30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 z80c30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 z85c30/z80c30 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 z85c30 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 z80c30 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3
ps011706-0511 list of figures cmos scc serial communications controller product specification vi list of figures figure 1. scc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. z85c30 and z80c30 dip pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. z85c30 and z80c30 plcc pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. z85c30 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. z80c30 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. scc transmit data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. scc receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. scc interrupt priority schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. scc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. detecting 5- or 7-bit synchronous characters . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. an sdlc loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. data encoding methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. sdlc frame status fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. sdlc byte counting detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. write register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. write register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. write register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. write register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. read register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. read register bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 21. read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 23. interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24. read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 25. write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 26. interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 27. standard test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 28. open-drain test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ps011706-0511 list of figures cmos scc serial communications controller product specification vii figure 29. z85c30 read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 30. z85c30 interrupt acknowledge timing diagram . . . . . . . . . . . . . . . . . . . . . 49 figure 31. z85c30 cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 32. z85c30 reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 33. z85c30 general timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 34. z85c30 system timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 35. z80c30 read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 36. z80c30 interrupt acknowledge timing diagram . . . . . . . . . . . . . . . . . . . . . 62 figure 37. z80c30 reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 38. z80c30 general timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 39. z80c30 system timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 40. 40-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 41. 44-pin plcc package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ps011706-0511 list of tables cmos scc serial communications controller product specification viii list of tables table 1. scc read register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. scc write register functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 4. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5. z80c30/z85c30 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6. z85c30 read/write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7. z85c30 general timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 8. z85c30 system timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 9. z85c30 read/write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 10. z80c30 read/write timing1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 11. z80c30 general timing1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 12. z80c30 system timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 13. z80c30/z85c30 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ps011706-0511 overview cmos scc serial communications controller product specification 1 overview the features of zilog?s z80c30 and z85c30 devices include: ? z85c30: optimized for nonmultiplexed bus microprocessors ? z80c30: optimized for multip lexed bus microprocessors ? pin-compatible to nmos versions ? two independent 0 to 4.1 mbps, full-duplex ch annels, each with separate crystal oscil- lator, baud rate generator (brg), and di gital phase-locked loop (dpll) for clock recovery ? multiprotocol operation under program control; programmable for nrz, nrzi or fm data encoding ? asynchronous mode with five to eight bits and one, one and one-half, or two stop bits per character, programmable clock f actor, break detection and generation; par- ity, overrun, and framing error detection ? synchronous mode with internal or external character synchronization on one or two synchronous characters and crc generation and checking with crc-16 or crc-ccitt preset to either 1s or 0s ? sdlc/hdlc mode with comprehensive fram e-level control, automatic zero inser- tion and deletion, i-field residue handlin g, abort generation and detection, crc generation and checking, and sdlc loop ? software interrupt ackn owledge feature (not available with nmos) ? local loopback and auto echo modes ? supports t1 digital trunk2 ? enhanced dma support (not available with nmos) 10 x 19-bit status fifo 14-bit byte counter ? speeds ? z85c3o: 8.5, 10, 16.384 mhz ? z80c3o: 8, 10 mhz other features for z85c30 only some of the features listed below are available by default. some of them (features with *) are disabled on default to ma intain compatibility with the existing serial communications controller (scc) design, and ?pro gram to enable through wr7?:
ps011706-0511 overview cmos scc serial communications controller product specification 2 ? new programmable wr7 (write register 7 prime) to enable new features ? improvements to support sdlc mode of synchronous communication: ? improve functionality to ea se sending back-to-back frames ? automatic sdlc opening flag transmission ? automatic tx underrun/eom latch reset in sdlc mode ? automatic rts deactivation ? txd pin forced high in sdlc nrzi mode after closing flag ? complete crc reception ? improved response to abor t sequence in status fifo ? automatic tx crc generator preset/reset ? extended read for write registers ? write data set-up timing improvement ? improved ac timing: ? 3 to 3.6 pclk access recovery time ? programmable dtr/req timing ? write data to falling edge of wr setup time requirement is now eliminated ? reduced int timing ? other features include: ? extended read function to read back the written value to the write registers ? latching rro during read ? rro, bit d7 and rr10, bit d6 now has reset default value
ps011706-0511 general description cmos scc serial communications controller product specification 3 general description the z80c30/z85c30 serial communications controller (scc), is a pin and software compatible cmos member of the scc family introduced by zilog in 1981. it is a dual- channel, multiprotocol data comm unications peripheral that easily interfaces with cpu?s with either multiplexed or nonm ultiplexed address/data buses. the advanced cmos process offers lower power consumption, higher performance, and superior noise immunity. the programming flexibility of the internal registers allow the scc to be configured to various serial communications applications. the many on-chip features such as baud rate generators (brg), digital phase locked loops (dpll), and crystal oscillators re duce the need for an external logic. additional features include a 10 x 19-bit stat us fifo and 14-bit byte counter to support high speed sdlc transfers using dma controllers. the scc handles asynchronous formats, sync hronous byte-oriented protocols such as ibm bisync, and synchronous bit-oriented pr otocols such as hdlc and ibm sdlc. this device supports virtually any serial data transfer application (for example, cassette, ? diskette, tape drives, etc.). the device generates and ch ecks crc codes in any sync hronous mode and can be ? programmed to check data integrity in variou s modes. the scc also contains facilities for modem controls in both channels. in applications where the se controls are not required, the modem controls can be used for general- purpose i/o. the daisy-chain interrupt hierar- chy is also supported. figure 1 displays a block diagram of the scc.
ps011706-0511 general description cmos scc serial communications controller product specification 4 figure 1.scc block diagram channel a exploded view databus control interrupt iei ieo intack int control cpu & dma bus interface control interrupt logic control interrupt logic channel b register channel a register rxda channel a channel b receive logic receive mux crc checker data decode & sync character detection rec. status fifo 3 byte rec. status fifo 3 byte sdlc frame status fifo 10 x 19 ctsa dcda synca rtsa dtra /reqa modem/control logic digital phase-locked loop baud rate generator crystal oscillator amplifier receive and transmit clock multiplexer transmit buffer transmit logic transmit mux data encoding & crc generation txda trxca rtxca
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 5 pin descriptions the following links refer to descriptions of the pin functions common to the z85c30 and z80c30 devices. ? ctsa, ctsb ? dcda, dcdb ? dtr/reqa, dtr/reqb ? iei ? ieo ? int ? intack ? pclk ? rxda, rxdb ? rtxca, rtxcb ? rtsa, rtsb ? synca, syncb ? txda, txdb ? trxca, trxcb ? w/reqa, w/reqb ? ctsa , ctsb clear to send (inputs, active low) . if these pins are programmed for auto enable functions, a low on the inputs enables the respective transm itters. if not programmed as auto enable, these pins can be used as general-purpose in puts. both inputs are schmitt- trigger buffered to accommoda te slow rise-time inputs. the scc detects pulses on these inputs and can interrupt the cpu on both logic level transitions. dcda , dcdb data carrier detect (inputs, active low) . these pins function as receiver enables if programmed for auto enable. otherwise, these pins are u sed as general-purpose input
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 6 pins. both pins are schmitt-trigger buffered to accommodate slow rise-time signals. the scc detects pulses on these pins and can interrupt the cpu on both logic level transitions. dtr / reqa , dtr / reqb data terminal ready/request (outputs, active low) . these outputs follow the state programmed into the dtr bit. they can also be used as general-purpose outputs or as request lines for a dma controller. iei interrupt enable in (input, active high) . iei is used with ieo to form an interrupt daisy-chain when there is more than one interrupt driven device. a high iei indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. ieo interrupt enable out (output, active high) . ieo is high only if iei is high and the cpu is not servicing the scc interrupt or the scc is not requesting an interrupt (interrupt acknowledge cycle only). ieo is connected to the next lower priority device?s iei input and thus inhibits interrupts from lower priority devices. int interrupt request (output, open-drain, active low) . this signal activates when the scc requests an interrupt. intack interrupt acknowledge (input, active low) . this signal indicates an active interrupt acknowledge cycle. during this cycle, th e scc interrupt daisy chain settles. when rd is active, the scc places an interrupt vector on the data bus (if iei is high). intack is latched by the rising edge of pclk. pclk clock (input) . this is the master scc clock used to synchronize internal signals. pclk is a ttl level signal. pclk is not required to have any phase relationship with the master system clock. the maximum transmit rate is 1/4 pclk.
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 7 rxda, rxdb receive data (inputs, active high) . these signals receive serial data at standard ttl levels. rtxca , rtxcb receive/transmit clocks (inputs, active low) . these pins can be programmed in sev- eral different operating modes. in each channel, rtxc can supply the receive clock, the transmit clock, clock for the baud rate gene rator, or the clock for the digital phase- locked loop. these pins can also be programmed for use with the respective sync pins as a crystal oscillator. the receive clock can be 1, 16, 32, or 64 times th e data rate in asyn- chronous modes. rtsa , rtsb request to send (outputs, active low) . when the request to send (rts) bit in write register 5 (see figure 9 on page 22) is set, the rts signal goes low. when the rts bit is reset in the asynchronous mode and auto en able is on, the signal goes high after the transmitter is empty. in synchronous mode, it strictly follows the state of the rts bit. when auto enable is off, the rts pins can be used as general-purpose outputs. synca , syncb synchronization (inputs or outputs, active low) . these pins function as inputs, ? outputs, or part of the crystal oscillator circu it. in the asynchronous receive mode (crystal oscillator option not selected), these pins are inputs similar to cts and dcd . in this mode, transitions on these lines affect the state of the synchronous/hunt status bits in read register 0 (see figure 8 on page 19) but have no other function. in external synchronization mo de with the crystal oscillator not selected, these lines also act as inputs. in this mode, sync must be driven low for two receive clock cycles after the last bit in the synchronou s character is received. character assembly begins on the ? rising edge of the receive clock imme diately preceding the activation of sync . in the internal synchroniza tion mode (monosync and bisync ) with the crystal oscillator not selected, these pins act as outputs and ar e active only during th e part of the receive clock cycle in which synchron ous characters are recognized . this synchronous condition is not latched. these outputs are active each time a synchronization pattern is recognized (regardless of character boundaries). in sdlc mode, these pins act as outputs and are valid on receipt of a flag.
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 8 txda, txdb transmit data (outputs, active high) . these output signals transmit serial data at stan- dard ttl levels. trxca , trxcb transmit/receive clocks (inputs or outputs, active low) . these pins can be ? programmed in several diff erent operating modes. trxc may supply the receive clock or the transmit clock in the input mode or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generato r, or the transmit clock in the output mode. w / reqa , w / reqb wait/request (outputs, open-drain when programmed for a wait function, driven high or low when programmed for a request function) . these dual-purpose outputs can be programmed as request lines for a dm a controller or as wait lines to synchronize the cpu to the scc data rate. the reset state is wait. z85c30 the following links refer to descriptions of the pin functions spec ific to the z85c30 device. ? a/b ? ce ? d7?d0 ? d/c ? rd ? wr ? a/ b channel a/channel b (input) . this signal selects the channel in which the read or write operation occurs.
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 9 ce chip enable (input, active low) . this signal selects the scc for a read or write opera- tion d7?d0 data bus (bidirecti onal, tri-state) . these lines carry data and command to and from the scc. d/ c data/control select (input) . this signal defines the type of information transferred to or from the scc. a high indicates a data transfer; a low indicates a command. rd read (input, active low) . this signal indicates a read operation and when the scc is selected, enables the scc?s bus drivers. duri ng the interrupt acknowledge cycle, this sig- nal gates the interrupt vector onto the bus if the scc is the highest priority device request- ing an interrupt. wr write (input, active low) . when the scc is selected, this signal indicates a write oper- ation. the coincidence of rd and wr is interpreted as a reset. z80c30 the following links refer to descriptions of the pin functions spec ific to the z80c30 device. ? ad7?ad0 ? as ? cs0 ? cs1 ? ds ? r/w
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 10 ad7?ad0 address/data bus (bidirectional, active high, tri-state) . these multiplexed lines carry register addresses to the scc as we ll as data or control information. as address strobe (input, active low) . addresses on ad7?ad0 ar e latched by the rising edge of this signal. cs0 chip select 0 (input, active low) . this signal is latched concurrently with the addresses on ad7?ad0 and must be active for the intended bus transaction to occur. cs1 chip select 1 (input, active high) . this second select signal must also be active before the intended bus transaction can occur. cs1 must remain active throughout the transaction. ds data strobe (input, active low) . this signal provides timing for the transfer of data into and out of the scc. if as and ds coincide, this confluence is interpreted as a reset. r/ w read/write (input) . this signal specifies whether the operation to be performed is a read or a write.
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 11 pin diagrams figure 2 displays the pin assignments for the z85c30 and z80c30 dip packages. figure 2.z85c30 and z80c30 dip pin assignments d1 d3 d5 d7 int ieo iei intack +5v w /reqa synca rtxca rxda trxca txda dtr /reqa rtsa ctsa dcda pclk d0 d2 d4 d6 rd wr a/b ce d/c gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 z85c30 ad1 ad3 ad5 ad7 int ieo iei intack +5v w /reqa synca rtxca rxda trxca txda dtr /reqa rtsa ctsa dcda pclk ad0 ad2 ad4 ad6 ds as r/w cs0 cs1 gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 z80c30
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 12 figure 3 displays the pin assignments for the z85c30 and z80c30 plcc packages. figure 3.z85c30 and z80c30 plcc pin assignments ieo z85c30 iei intack +5v w /reqa synca rtxca rxda trxca txda nc a/b ce d/c nc gnd w /reqb syncb rtxcb rxdb trxcb txdb int d7 d5 d3 d1 d0 d2 d4 d6 rd wr nc dtr /reqa rtsa ctsa dcda pcld dcdb ctsb rtsb dtr /reqb nc 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 39 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 ieo z80c30 iei intack +5v w /reqa synca rtxca rxda trxca txda nc r/w cs0 cs1 nc gnd w /reqb syncb rtxcb rxdb trxcb txdb int ad7 ad5 ad3 ad1 ad0 ad2 ad4 ad6 ds as nc dtr /reqa rtsa ctsa dcda pclk dcdb ctsb rtsb dtr /reqb nc 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 39 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 13 figures 4 and 5 display the pin functions for the z85c30 and z80c30 devices, respec- tively. descriptions for each of these pins can be found in the functional descriptions chapter on page 15. figure 4.z85c30 pin functions z85c30 serial data channel clocks ch-a channel controls for modem, dma and other ch-b serial data channel clocks channel controls for modem, dma and other data bus d7 d6 d5 d4 d3 d2 d1 d0 rd wr a/b ce d/c int intack iei ieo txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb rxdb trxcb and reset control interrupt bus timing
ps011706-0511 pin descriptions cmos scc serial communications controller product specification 14 figure 5.z80c30 pin functions z80c30 serial data channel clocks ch-a channel controls for modem, dma and other ch-b serial data channel clocks channel controls for modem, dma and other data bus ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 as ds r/w cs1 cs0 int intack iei ieo txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb rxdb trxcb and reset control interrupt bus timing
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 15 functional descriptions the architecture of the scc device functions as: ? a data communications device which transmits and receives data in various protocols ? a microprocessor peripheral in which the s cc offers valuable features such as vec- tored interrupts and dma support ? the scc?s peripheral and data communication features are described in the following sec- tions. figure 1 on page 4 displays the scc block diagram. figures 6 and 7 display the details of the communication between the receive and tran smit logic to the system bus. the features and data path for each of the s cc?s a and b channels are identical. figure 6. scc transmit data path from receiver crc-gen zero insert (5 bits) 20-bit tx shift register sync register sync register internal data bus to other channel internal txd txd nrz encode transmit mux & 2-bit delay transmit clock tx buffer 1 byte final tx mux wrb wr6 sync sync sdlc wr7
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 16 i/o interface capabilities system communication to and from the scc de vice is performed through the scc?s regis- ter set. there are sixteen write registers and eight read registers. throughout this document, write and read re gisters are referenced with the following notation: ? ?wr? for write register ? ?rr? for read register ? figure 7. scc receive data path to transmit section mux nrzi decode mux internal txd dpll sync register & zero delete out sdlc-crc crc checker crc result sync crc crc delay register (8 bits) receive shift register 3-bit rxd dpll in dpll 1-bit hunt mode (bisync) 14-bit counter rec. error logic brg output rec. error fifo 3 byte deep rec. error fifo 3 byte deep status fifo 10 x 19 frame i/o data buffer internal data bus cpu/i/o brg input 16-bit down counter div 2 upper byte (wr13) time constant lower byte (wr12) time constant
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 17 for example, wr4a write register 4 for channel a rr3 read register 3 for either/both channels ? tables 1 and 2 list the scc registers and provide a brief description of their functions. table 1. scc read register functions register function rr0 transmit/receive buffer st atus and external status rr1 special receive condition status rr2 modified interrupt vector (channel b only) unmodified interrupt vector (channel a only) rr3 interrupt pending bits (channel a only) rr8 receive buffer rr10 miscellaneous status rr12 lower byte of baud rate generator time constant rr13 upper byte of baud rate generator time constant rr15 external/status in terrupt information table 2. scc write register functions register function wr0 crc initialize, initializ ation commands for the various modes, register pointers wr1 transmit/receive interrupt and data transfer mode definition wr2 interrupt vector (accessed through either channel) wr3 receive parameters and control wr4 transmit/receive miscellaneous parameters and modes wr5 transmit parameters and controls wr6 sync characters or sdlc address field wr7 sync character or sdlc flag wr7* extended feature and fifo control (wr7 prime) 85c30 only wr8 transmit buffer wr9 master interrupt control and reset (accessed through either channel) wr10 miscellaneous transmi tter/receiver control bits wr11 clock mode control wr12 lower byte of baud rate generator time constant
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 18 the following three methods move data, status and control information in and out of the scc; each is described in this section. ? polling ? interrupts (vectored and nonvectored) ? cpu/dma block transfer , in which block transfer mode can be implemented under cpu or dma control polling when polling, all interrupts ar e disabled. three status registers in the scc are automati- cally updated when any function is perform ed. for example, end-of-frame in sdlc mode sets a bit in one of these status registers. the purpose of polling is for the cpu to periodically read a status register until the regist er contents indicate the need for data to be transferred. only one register is read, and de pending on its contents, the cpu either writes data, reads data, or continues. two bits in th e register indicate the need for data transfer. an alternative is a poll of the interrupt pend ing register to determine the source of an interrupt. the status for both ch annels resides in one register. interrupts the scc?s interrupt structure supports vector ed and nested interrupt s. nested interrupts are supported with the interrupt acknowledge feature (intack pin) of the scc. this allows the cpu to recognize the occurrenc e of an interrupt, and reenable higher pri- ority interrupts. because an intack cycle releases the int pin from the active state, a higher priority scc interrupt or another higher priority device can interrupt the cpu. when an scc responds to an interrupt acknowledge signal (intack ) from the cpu, an interrupt vector can be placed on the data bu s. this vector is written in wr2 and can be read in rr2a or rr2b. to speed interrupt re sponse time, the scc ca n modify three bits in this vector to indicate status. if the vector is read in channel a, status is never included. if the vector is read in channel b, status is always included. each of the six sources of interrupts in the scc (transmit, receive, and external/status interrupts in both channels) has three b its associated with the interrupt source. wr13 upper byte of baud ra te generator time constant wr14 miscellaneous control bits wr15 external/status interrupt control table 2. scc write register functions (continued) register function
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 19 interrupt pending (ip), interrupt under service (ius), and in terrupt enable (ie). opera- tion of the ie bit is straight forward. if the ie bit is set for a given interrupt source, then that source can request interrupts. the exce ption is when the mie (master interrupt enable) bit in wr9 is reset and no interrupts ca n be requested. the ie bits are write only. the other two bits are related to the interrupt priority chain (see figure 8 on page 19). as a microprocessor peripheral, the scc can request an interrupt only when no higher priority device is requesting one, that is, when iei is high. if the device in question requests an interrupt, it pulls down int . the cpu responds with intack , and the interrupting device places the vector on the data bus. figure 8. scc interrupt priority schedule the scc can also execute an interrupt acknowledge cycle through soft ware. in some cpu environments, it is difficult to create the intack signal with the necessary timing to acknowledge interrupts and allo w the nesting of interrupts. in these cases, the intack signal can be created with a software command to the scc. in the scc, the interrupt pending (ip) bit signals a need for interrupt servicing. when an ip bit is 1 and the iei input is high, the int output is pulled low, requesting an interrupt. in the scc, if the ie bit is not set by enabling interrupts, then the ip for that source is never set. the ip bits are readable in rr3a. the ius bits signal that an interrupt request is being serviced. if an ius is set, all interrupt sources of lower priority in the scc and ex ternal to the scc are prevented from request- ing interrupts. the internal interrupt sources ar e inhibited by the state of th e internal daisy chain, while lower priority devices are in hibited by the ieo output of the scc being pulled low and propagated to subsequent peripherals. an ius bit is set during an interrupt acknowledge cycle, if there are no higher pr iority devices requ esting interrupts. there are three types of interrupts: ? transmit ? receive +5 v +5 v d7?d0 int intack iei d7?d0 int intack ieo iei d7?d0 int intack ieo iei d7?d0 int intack peripheral peripheral peripheral
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 20 ? external/status ? each interrupt type is enabled under program control with channel a having higher prior- ity than channel b, and with receiver, transm it, and external/status interrupts prioritized in that order within each channel. when enabled, the recei ver interrupts the cpu in one of three ways: ? interrupt on first receive character or special receive condition ? interrupt on all receive charact ers or special receive conditions ? interrupt on special receive conditions only ? interrupt on first character or special condition and interru pt on special condition only are typically used with the block transfer mo de. a special receive co ndition is one of the following. receiver overrun, framing error in asynchronous mode, end-of-frame in sdlc mode and, optionally, a parity error. the sp ecial receive condition interrupt is different from an ordinary receive character available inte rrupt only by the status placed in the vec- tor during the interrupt ackno wledge cycle. in interrupt on first receive character, an interrupt occurs from special receive conditions anytime afte r the first receive character interrupt. the main function of the extern al/status interrupt is to mon itor the signal transitions of the cts , dcd , and sync pins, however, an external/statu s interrupt is also caused by a transmit underrun condition; a zero count in the baud rate gene rator; by the detection of a break (asynchronous mode), abort (sdlc mode) or eop (sdlc loop mode) sequence in the data stream. the interrupt ca used by the abort or eop has a special fea- ture allowing the scc to interrupt when the abort or eop sequence is detected or termi- nated. this feature facilitat es the proper termination of the current message, correct initialization of the next messag e, and the accurate timing of the abort condition in exter- nal logic in sdlc mode. in sd lc loop mode, this feature al lows secondary stations to recognize the primary station regaining co ntrol of the loop during a poll sequence. software interrupt acknowledge on the cmos version of the scc, the scc interrupt acknowledge cycle can be initiated through software. if write register 9 (wr9) bit d5 is set, read register 2 (rr2) results in an interrupt acknowledge cycl e to be executed internally. like a hardware intack cycle, a software acknowledge causes the int pin to return high, the ieo pin to go low and set the ius latch for the highest priority interrupt pending. similar to using the hardware intack signal , a software acknowledge cycle requires that a reset highest ius command be issued in the interrupt service routine. whenever an interrupt acknowledge cycle is used, hardware or software, a reset highest ius command is required. if rr2 is read from channel a, th e unmodified vector is returned. if rr2 is read from channel b, then the vector is modi fied to indicate the source of the interrupt.
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 21 the vector includes status (vis) and no vect or (nv) bits in wr9 are ignored when bit 05 is set to 1. when the intack and iei pins are not being used, they should be pulled up to v cc through a resistor (10 k ? typical). cpu/dma block transfer the scc provides a block transfer mode to accommodate cpu block transfer functions and dma controllers. the bloc k transfer mode uses the wait /reouest output in con- junction with the wait/request bits in wr1. the wait /reouest output can be defined under software control as a wait lin e in the cpu block transfer mode or as a request line in the dma block transfer mode. to a dma controller, the scc request output indicates that the scc is ready to trans- fer data to or from memory to the cpu, the wait line indicates that the escc is not ready to transfer data, thereby requesting th at the cpu extend the i/o cycle. the dtr / request line allows full-duplex operation under dma control.
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 22 scc data communications capabilities the scc provides two independ ent full-duplex programmable channels for use in any common asynchronous or synchronous data comm unication protocols; see figure 9. each data communication channel has id entical feature and capabilities. asynchronous modes send and receive is accomplished independently on each channel with five to eight bits per character, plus optional even or odd par ity. the transmitters can supply one, one-and- a-half, or two stop bits per character and can provide a break output at any time. the receiver break-detection logic interrupts the cp u both at the start and at the end of a received break. reception is protected from spikes by a tran sient spike-rejection mechanism that checks the signal one-half a bit time af ter a low level is detected on the receive data input (rxda or rxdb pins). if the low does not persist (a transient), the character assembly process does not start. figure 9. scc protocols flag address information crc1 crc2 information flag data sync crc1 signal crc1 crc2 marking line data crc2 sync data data crc1 crc2 sync data data start sdlc/hdlc/x.25 parity stop data data data marking line external sync bisync monosync asynchronous
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 23 framing errors and overrun errors are detected and buffered to gether with the partial char- acter on which they occur. vectored interrupt s allow fast servicing or error conditions using dedicated routines. a built-in checking process avoids the interpretation of a fram- ing error as a new start bit. a framing error re sults in the addition of one-half a bit time to the point at which the search for the next start bit begins. the scc does not require symmetric transmit and receive clock signals ? a feature that allows the use of a wide variety of clock so urces. the transmitter and receiver handle data at a rate supplied to the receive and transm it clock inputs. in asynchronous modes, the sync pin can be programmed as an input used for functions such as monitoring a ring indicator. synchronous modes the scc supports both byte and bit-orient ed synchronous communication. synchronous byte-oriented protocols are handled in several modes. they allow character synchroniza- tion with a 6-bit or 8-bit sync character (m onosync), and a 12-bit or 16-bit synchroniza- tion pattern (bisync), or with an external sync signal. leading sync characters are removed without interrupting the cpu. 5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the scc by overlapping the larger pattern across multiple incoming synchronous characters, as shown in figure 10. crc checking for synchronous byte-oriented mo des is delayed by on e character time so that the cpu can disable crc checking on sp ecific characters. this feature permits the implementation of protocols such as ibm bisync. both crc-16 (x 16 + x 15 + x 12 +1) and ccitt (x 16 + x 12 + x 5 + 1) error-checking polynomials are supporte d. either polynomial can be sel ected in all synchronous modes. you can preset the crc generator and checker to all 1?s or all 0?s. the scc also provides a feature that automatically transmits crc data when no other data is available for trans- figure 10. detecting 5- or 7-bit synchronous characters data data data data sync sync 7 bits 8 16 sync
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 24 mission. this feature allows for high spee d transmissions under dm a control, with no need for cpu intervention at the end of a message. when there is no data or crc to send in sy nchronous modes, the transmitter inserts 6-,8-, or 16-bit sync characters, regardless of the programmed character length. sdlc mode the scc supports synchronous bit-oriented protocols, such as sdlc and hdlc, by per- forming automatic flag sending, zero insertion, and crc generation. a special command is used to abort a frame in transmission. at the end of a message, the scc automatically transmits the crc and trailing flag when the transmitter underruns. the transmitter can also be programmed to send an idle line consisting of continuous flag characters or a steady marking condition. if a transmit underrun occurs in the middle of a message, an externa l/status interrupt warns the cpu of this status change, issuing an ab ort. the scc can also be programmed to send an abort itself in case of an underrun, relievin g the cpu of this task. one to eight bits per character can be sent, allowing reception of a message with no prior information about the character structure in the information field of a frame. the receiver automatically acqu ires synchronization on the leading flag of a frame in sdlc or hdlc and provides a synchronization signal on the sync pin (an interrupt can also be programmed). the rece iver can be programmed to search for frames addressed by a single byte (or four bits within a byte) of a user-selected address or to a global broadcast address. in this mode, frames not matching e ither the user-selected or broadcast address are ignored. the number of address bytes are extended unde r software control. for receiving data, an interrupt on the first received character, or an interrupt on every character, or on special condition only (end-of-frame) can be selected. th e receiver automatically deletes all 0?s inserted by the transmitter during character assembly crc is also cal culated and is auto- matically checked to validate frame transmission . at the end of transmission, the status of a received frame is available in the status registers. in sdlc mode, the scc must be pro- grammed to use the sdlc crc polynomial, bu t the generator and checker can be preset to all 1?s or all 0?s. the crc inverts before transmission and the receiver checks against the bit pattern 0001110100001111 . nrz, nrzi or fm coding can be used in any 1 x mode. the parity options available in asynchronous modes are available in synchronous modes. sdlc loop mode the scc supports sdlc loop mode in add ition to normal sdlc. in an sdlc loop, a primary controller station manages the message traffic flow on the loop and any number of secondary stations. in sdlc loop mode, th e scc performs the functions of a secondary station while an scc operating in regular sd lc mode acts as a controller; see figure 11. the sdlc loop mode can be selected by setting wr10 bit d1.
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 25 a secondary station in an sdlc loop is alwa ys listening to the me ssages sent around the loop and passes these messages to the rest of the loop by retransmitting them with a one- bit-time delay. the secondary station places its own message on the loop only at specific times. the controller signals that secondary stations can transmit messages by sending a special character, called an end of poll (eop), arou nd the loop. the eop character is the bit pat- tern 11111110 . because of zero insertion during messa ges, this bit pattern is unique and easily recognized. when a secondary station contains a message to transmit and recognizes an eop on the line, it changes the last binary 1 of the eop to a 0 before transmission. this change has the effect of turning the eop into a flag seque nce. the secondary station now places its mes- sage on the loop and terminates the message w ith an eop. any secondary stations further down the loop with messages to transmit append their messages to the message of the first secondary station by the same process. any s econdary stations without messages to send echo the incoming message and are prohibite d from placing messages on the loop (except when recognizing an eop). in sdlc loop mode, nrz, nrzi, and fm coding can be used. the scc?s ability to receive high speed back -to-back sdlc frames is maximized by a 10- deep by 19-bit wide status fifo. when enabled (through wr15, bit d2), it provides the dma the ability to continue to transfer data into memory so that the cpu can examine the figure 11. an sdlc loop secondary #2 secondary #3 secondary #4 controller secondary #1
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 26 message later. for each sdlc frame, a 14-bit by te count and 5 status/error bits are stored. the byte count and status bits are accessed through read registers 6 and 7. read regis- ters 6 and 7 are only accessible when the sdlc fifo is enabled. the 10 x 19 status fifo is separate from the 3-byte receive data fifo. baud rate generator each channel in the scc contains a programmable baud rate ge nerator (brg). each generator consists of two 8-bit time constant registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output producing a square wave. on startup, the output flip-flop is set in a high state, the va lue in the time constant register is loaded into the counter, and the co unter starts counting down. the output of the brg toggles when reaching 0, the value in the time constant register is loaded into the counter, and the process is repeated. the time constant can be changed at any time, but the new value does not take effect until the ne xt load of the counter. the output of the brg can be used as either th e transmit clock, the receive clock, or both. it can also drive the digital phase-locked loop (see digital phase-locked loop ). if the receive clock or transmit clock is not pr ogrammed to come from the trxc pin, the output of the brg can be echoed out through the trxc pin. the following formula relates the time constant to the baud rate where pclk or rtxc is the brg input frequency in hertz. the clock mode is 1, 16, 32, or 64, as selected in write register 4, bits d6 and d7. synchronous operation modes select 1 and asynchronous modes select 16, 32 or 64. digital phase-locked loop the scc contains a digital phase-locked loop (dpll) to recover clock information from a data stream with nrzi or fm encodi ng. the dpll is driven by a clock that is nominally 32 (nrzi) or 16 (fm) times the data rate. the dpll uses this clock, along with the data stream, to construct a clock for the data. this cloc k is used as the scc receive clock, the transmit clock, or both. when the dp ll is selected as the transmit clock source, it provides a jitter-free clock output that is the dpll input frequency divided by the appropriate divisor for the selected encoding technique. for nrzi encoding, the dpll co unts the 32x clock to creat e nominal bit times. as the 32x clock is counted, the dpll is searching the incoming data stream for edges (either 1 to 0, or 0 to 1). whenever an edge is det ected, the dpll makes a count adjustment (during the next counting cycle), producing a terminal count closer to the center of the bit cell. time constant = pclk or rtxc frequency 2(baud rate)(clock mode) -2
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 27 for fm encoding, the dpll agai n counts from 0 to 31, but w ith a cycle corresponding to two bit times. when the dpll is locked, the clock edges in th e data stream occur between counts 15 and 16 and between counts 31 and 0. the dpll looks for edges only during a time centered on the 15 to 16 counting transition. the 32x clock for the dpll can be programmed to come from either the rtxc input or the output of the brg. the dpll output can be programmed to be echoed out of the scc through the trxc pin (if this pin is not being used as an input). data encoding the scc can be programmed to encode and deco de the serial data in four different meth- ods; see figure 12. in nrz encoding, a 1 is represented by a high level and a 0 is repre- sented by a low level. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. in fm1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit cell. a 1 is represented by an additional transition at the cente r of the bit cell and a 0 is rep- resented by no additional transiti on at the center of the bit cell. in fm0 (bi-phase space), a transition occurs at the beginning of every bit cell. a 0 is repre- sented by an additional transition at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. in addition to these four meth ods, the scc can be used to decode manchester (bi-phase level) data by using the dpll in the fm mode and progra mming the receiver for nrz data. manchester encoding always produces a transition at the center of the bit cell. if the transition is 0 to 1, the bit is a 0. if the transition is 1 to 0, the bit is a 1.
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 28 auto echo and local loopback the scc is capable of automati cally echoing everything it receives. this feature is useful mainly in asynchronous modes, but works in synchronous and sdlc modes as well. auto echo mode (tx0 is rx0) is used with nrzi or fm encoding with no additional delay because the data stream is not decoded before retransmission. in auto echo mode, the cts input is ignored as a transmitter enable (although transitions on this input can still cause interrupts if programmed to do so). in this mode, the transmitter is actually bypassed and the programmer is responsible for disabling transmitter interrupts and wait / request on transmit. the scc is also capable of local loopback. in this mode, txd or rx d is similar to auto echo mode. however, in local loopback mode the internal tr ansmit data is tied to the internal receive data and rxd is ignored (except to be echoed out through txd). the cts and dcd inputs are also ignored as transmit and receive enables. however, transitions on these inputs can still cause in terrupts. local loopback works in asynchronous, synchro- nous and sdlc modes with nrz, nrzi or fm coding of the data stream. sdlc fifo frame sta tus fifo enhancement the scc?s ability to receive high speed back-t o-back sdlc frames is maximized by a 10- deep by 19-bit wide status fifo. when enabled (through wr15, bit d2), it provides the figure 12. data encoding methods data nrz nrzi fm1 fm0 manchester 110 0 0 1
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 29 dma the ability to continue to transfer data into memory so that the cpu can examine the message later. for each sdlc frame, a 14-bit by te count and 5 status/error bits are stored. the byte count and status bits are accessed through read registers 6 and 7. read regis- ters 6 and 7 are only accessible when the sdlc fifo is enabled. the 10x19 status fifo is separate from the 3-byte receive data fifo. when the enhancement is enable d, the status in read register 1 (rr1) and byte count for the sdlc frame are stored in the 10 x 19 b it status fifo. this arrangement allows the dma controller to transfer the next frame into memory while the cpu verifies that the message was properly received. summarizing the operation; data is received, assembled, and loaded into the eight byte fifo before being transferred to memory by the dma controlle r. when a flag is received at the end of an sdlc frame, the frame byte count from the 14-bit counter and five status bits are loaded into the status fifo for verification by the cpu. the crc checker auto- matically resets in preparation for the next frame which can begin immediately. because the byte count and status are saved for each fra me, the message integrity is verified at a later time. the status information for up to 10 frames is stored before a status fifo over- run occurs. if a frame is terminated with an abort, the byte count is loaded to the status fifo and the counter resets for the next frame. fifo detail for more details about fifo operation, see figure 13 on page 30 . enable/disable this fifo is implemented is enabled when wr15, bit d2, is set and the scc is in the sdlc/hdlc mode. otherwise, the status re gister contents bypass the fifo and go directly to the bus interface (the fifo poin ter logic is reset either when disabled or through a channel or power-on reset). when the fifo mode is disabled, the scc is downward-compatible with th e nmos z8530. the fifo mode is disabled on power-up (wr15 d2 is set to 0 on reset). the effects of backward compatibility on the register set are that rr4 is an image of rr0, rr5 is an image of rr1, rr6 is an image of rr2 and rr7 is an image of rr3. for more details about the added registers, see figure 16 on page 34. the status of the fifo enable signal is obtained by reading rr15, bit d2. if the fifo is enabled, the bit is set to 1; otherwise, it resets. read operation when wr15 bit d2 sets and the fifo is not empt y, the next read to status register rr1 or registers rr7 and rr6, is from the fifo. read ing status register rr1 causes one location of the fifo to become empty. status is read after reading the byte count, otherwise the count is incorrect. before the fifo underflows, it is disabled . in this case, the multiplexer is switched allowing status to read directly from the status register. reads from rr7 and
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 30 rr6 contain bits that are undefined. bit d6 of rr7 (fifo data available) determines if status data is coming from the fifo or dire ctly from the status register, which sets to 1 when the fifo is not empty. not all status bits are stored in the fifo. the all sent, parity, and eof bits bypass the fifo. status bits sent through the fifo are residue bits (3), overrun, and crc error. figure 13. sdlc frame status fifo over equal reset on flag detect increment on byte detection enable count in sdlc end of frame signal status read comp tail pointer 4-bit counter head pointer 4-bit counter 4-bit comparator 14 bits byte counter frame status fifo circuitry 5 bits fifo array 10 deep by 19 bits wide scc status reg residue bits (3) overrun, crc error rr1 5 bits en 6 bits 8 bits 6-bit mux 2 bits eof = 1 6 bits rr1 bit 7 bit 6 bits 5-0 rr6 fifo enable rr7 d5-d0 + rr6 d7-d0 byte counter contains 14 bits for a 16 kbyte maximum count rr7 d6 fifo data available status bit status bit set to 1 when reading from fifo rr7 d7 fifo overflow status bit msb pf rr(7) is set on status fifo overflow wr(15) bit 2 set enables status fifo in sdlc mode the following definitions apply interface to scc
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 31 the sequence for operation of the byte count and fifo logic is to read the registers in the following order. rr7, rr6, an d rr1 (reading rr6 is optional) . additional logic prevents the fifo from being emptied by multiple read s from rr1. the read from rr7 latches the fifo empty/full status bit (d6) and steers the status multiplexer to read from the scc megacell instead of the status fifo (since the status fifo is empty). the read from rr1 allows an entry to be read from the fifo (i f the fifo was empty, logic was added to pre- vent a fifo underflow condition). write operation when the end of an sdlc frame (eof) is rece ived and the fifo is enabled, the contents of the status and byte-count registers are loaded into the fifo. the eo f signal is used to increment the fifo. if the fifo overflows, rr7, bit d7 (fifo overflow) sets to indicate the overflow. this bit and the fifo control lo gic is reset by disabling and reenabling the fifo control bit (wr15, bit 02). for details of fifo control timing during an sdlc frame, see figure 14. programming the scc contains write registers in each channel that are programmed by the system sep- arately to configure the functional personality of the channels. z85c30 in the scc, the data registers are directly addressed by selecting a high on the d/ c pin. with all other registers (except wr0 and rr0) , programming the write registers requires two write operations and readin g the read registers requires both a write and a read oper- ation. the first write is to wr0 and contains th ree bits that point to the selected register. figure 14. sdlc byte counting detail don?t load counter on 1st flag reset byte counter here reset byte counter load counter into fifo and increment ptr internal byte strobe increments counter reset byte counter internal byte strobe increments counter reset byte counter load counter into fifo and increment ptr f a dd d d c c f 0 7 0 f ad d dd c c f 07 0
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 32 the second write is the actual control word for the selected register, and if the second operation is read, the selected read register is accessed. all the scc registers, including the data registers, can be accessed in this fashion. the pointer bits are automatically cleared after the read or write operation so that wr0 (or rr0) is addressed again. z80c30 all scc registers are directly addressable. a command issued in wr0b controls how the scc decodes the address placed on the address/ data bus at the beginning of a read or write cycle. in the shift right mode, the ch annel select a/b is taken from ad0 and the state of ad5 is ignored. in the shift left mode, the channel select a/b is taken from ad5 and the state of ad0 is ignored. ad7 and ad6 are always ignored as address bits and the register address occupies ad4-ad1. z85c30/z80c30 setup initialization the system program first issues a series of commands to initiali ze the basic mode of ? operation. this is followed by other comm ands to qualify conditi ons within the selected mode. for example, in the asynchronous mode , character length, clock rate, number of stop bits, and even or odd parity must be set fi rst. the interrupt mode is set, and finally, the receiver and transmitter are enabled. write registers the scc contains 15 write registers for the 80c30, while there are 16 for the 85c30 (one more additional write register if counting th e transmit buffer) in each channel. these write registers are programmed separately to configure the functional ?perso nality? of the channels. there are two registers (wr2 and wr9) shared by the two channels that are accessed through either of them. wr2 contai ns the interrupt vector for both channels, while wr9 contains the interrupt control bits and reset commands. figures 15 through 18 display the format of each write register.
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 33 figure 15. write register bit functions register 0 * 0 0 0 1 1 0 1 1 0 0 01 1 0 1 1 null code null code null code null code null code * b channel only reset rx crc checker reset tx crc checker reset tx underrun/eom latch reset ext/status interrupts send abort enable int on next rx character reset tx int pending error reset reset highest ius select shift left mode select shift right mode 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 write register 0 (multiplexed bus mode) d7 d6 d5 d4 d3 d2 d1 d0 write register 0 (non-multiplexed bus mode) null code 0 0 0 1 1 0 1 1 * with point high command reset rx crc checker reset tx crc generator reset tx underrun/eom latch register 1 register 2 register 3 register 4 register 5 register 6 register 7 register 8 register 9 register 10 register 11 register 12 register 13 register 14 register 15 * 000 00 00 0 00 0 0 00 0 0 0 00 0 0 0 0 0 11 1 1 1 11 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 000 00 00 0 00 0 0 1 11 1 1 1 1 1 1 1 1 1 null code point high reset ext/status interrupts send abort (sdlc) enable int on next rx character reset tx int pending error reset reset highest ius d7 d6 d5 d4 d3 d2 d1 d0 write register 1 0 0 0 0 1 1 1 1 ext int enable tx int enable parity is special condition rx int on special condition only int on all rx characters or special condition rx int on first character or special condition wait/dma request on receive /transmit rx int disable wait /dma request function wait/dma request d7 d6 d5 d4 d3 d2 d1 d0 write register 2 v0 v1 v2 v3 v4 v5 v6 v7 interrupt vector d7 d6 d5 d4 d3 d2 d1 d0 write register 3 rx enable sync character load inhibit address search mode (sdlc) rx crc enable enter hunt mode auto enables 0 0 0 0 1 1 1 1 rx 5 bits/character rx 7 bits/character rx 6 bits/character rx 8 bits/character
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 34 figure 16. write register bit functions d7 d6 d5 d4 d3 d2 d1 d0 write register 4 parity enable parity even/odd 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 sync modes enable 1 stop bit/character 1 1/2 stop bits/character 2 stop bits/character 8-bit sync character 16-bit sync character sdlc mode (011 11110 flag) external sync mode x1 clock mode x16 clock mode x32 clock mode x64 clock mode d7 d6 d5 d4 d3 d2 d1 d0 write register 5 0 0 0 0 1 1 1 1 tx crc enable rts sdlc /crc-16 tx enable send break dtr tx 5 bits (or less)/character tx 7 bits/character tx 6 bits/character tx 8 bits/character
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 35 figure 17. write register bit functions d7 d6 d5 d4 d3 d2 d1 d0 write register 6 sync7 sync1 sync7 sync3 adr7 adr7 sync6 sync0 sync6 sync2 adr6 adr6 sync5 sync5 sync5 sync1 adr5 adr5 sync4 sync4 sync4 sync0 adr4 adr4 sync3 sync3 sync3 1 x adr3 sync2 sync2 sync2 1 x adr2 sync1 sync1 sync1 1 x adr1 sync0 sync0 sync0 1 x adr0 monosync, 8 bits monosync, 6 bits bisync, 16 bits bisync, 12 bits sdlc sdlc (address range) d7 d6 d5 d4 d3 d2 d1 d0 write register 7 sync7 sync5 sync15 sync11 monosync, 8 bits monosync, 6 bits bisync, 16 bits bisync, 12 bits sdlc 0 sync6 sync4 sync14 sync10 1 sync5 sync3 sync13 sync9 1 sync4 sync2 sync12 sync8 1 sync3 sync1 sync11 sync7 1 sync2 sync0 sync10 sync6 1 sync1 x sync9 sync5 1 sync0 x sync8 sync4 0 d7 d6 d5 d4 d3 d2 d1 d0 wr 7? prime (85c30 only) auto tx flag auto eom reset auto rts deactivation force txd high dtr /req fast mode complete crc reception extended read enable reserved (program as 0)
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 36 figure 18. write register bit functions 0 0 0 0 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 write register 9 no reset channel reset b channel reset a force hardware reset vis nv dlc mie status high/status low software intack enable d7 d6 d5 d4 d3 d2 d1 d0 write register 10 0 0 0 0 1 1 1 1 nrz nrzi fm1 (transition = 1) fm1 (transition = 0) crc preset i/o go active on poll mark/flag idle abort/flag on underrun loop mode 6-bit/8-bit sync d7 d6 d5 d4 d3 d2 d1 d0 write register 11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 trxc out = xtal output trxc out = transmit clock trxc out = br generator output trxc out = dpll output trxc o/i transmit clock = rtxc pin transmit clock = trxc pin transmit clock = br generator output transmit clock = dpll output receive clock = rtxc pin receive clock = trxc pin receive clock = br generator output receive clock = dpll output rtxc xtal/no xtal d7 d6 d5 d4 d3 d2 d1 d0 write register 12 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 lower byte of time constant upper byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 write register 13 tc8 tc9 tc10 tc11 tc12 tc13 tc14 tc15 d7 d6 d5 d4 d3 d2 d1 d0 write register 14 br generator enable br generator source dtr /request function auto echo local loopback 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 11 1 1 1 1 1 null command enter search mode reset missing clock disable dpll set source = br generator set source = rtxc set fm mode set nrzi mode d7 d6 d5 d4 d3 d2 d1 d0 write register 15 0 zero count ie sdlc fifo enable dcd ie sync/hunt ie cts ie tx underrun/eom ie break/abort ie
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 37 read registers the scc contains ten read registers (eleven, counting the receive buffer (rr8) in each channel). four of these can be read to ob tain status information (rr0, rr1, rr10, and rr15). two registers (rr12 and rr13) are read to learn the baud rate generator time constant. rr2 contains either the unmodified interrupt vector (channel a) or the vector modified by status information (channel b). rr3 contains the interru pt pending (ip) bits (channel a only; see figure 19). rr6 and rr7 contain the information in the sdlc frame status fifo, but is only read when wr15 d2 is set (see figures 19 and 20 ). figure 19. read register bit functions d7 d6 d5 d4 d3 d2 d1 d0 read register 0 rx character available zero count tx buffer empty dcd sync/hunt cts tx underrun/eom break/abort d7 d6 d5 d4 d3 d2 d1 d0 read register 1 all sent residue code 2 residue code 1 residue code 0 parity error rx overrun error crc/framing error end of frame (sdlc) d7 d6 d5 d4 d3 d2 d1 d0 read register 2 v0 v1 v2 v3 v4 v5 v6 v7 interrupt vector * * modified in b channel d7 d6 d5 d4 d3 d2 d1 d0 read register 12 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 lower byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 read register 10 0 on loop 0 0 loop sending 0 two clocks missing one clocks missing d7 d6 d5 d4 d3 d2 d1 d0 read register 3 channel b ext/status ip channel b tx ip channel b rx ip channel a ext/status ip channel a tx ip channel a rx ip 0 0 * * always 0 in b channel
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 38 z85c30 timing the scc generates internal control signals from the wr and rd that are related to pclk. pclk has no phase relationship with wr and rd , the circuitry genera ting the internal control signals provides time for meta-stable conditions to disa ppear. this gives rise to a recovery time related to pclk. the recovery time applies only betw een bus transactions involving the scc. the recovery time requ ired for proper operation is specified from the falling edge of wr or rd in the first transaction involving the scc to the falling edge of wr or rd in the second transaction involving the scc. this time must be at least 3 pclks regardless of which register or channel is being accessed. the z85c30 timings are described below: ? read cycle timing ? write cycle timing ? interrupt acknowledge cycle timing ? figure 20. read register bit functions d7 d6 d5 d4 d3 d2 d1 d0 read register 13 tc8 tc9 tc10 tc11 tc12 tc13 tc14 tc15 upper byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 read register 15 0 zero count ie 0 dcd ie sync/hunt ie cts ie tx underrun/eom ie break/abort ie
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 39 read cycle timing figure 21 displays read cy cle timing. addresses on a/ b and d/c and the status on intack must remain stable throughout the cycle. if ce falls after rd falls, or if ce rises before rd rises, the effective rd is shortened. figure 21. read cycle timing d7?d0 data valid rd ce intack a/ b , d/c address valid
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 40 write cycle timing figure 22 displays write cycle timing. addresses on a/b and d/c and the status on intack must remain stable th roughout the cycle. if ce falls after wr falls, or if ce rises before wr rises, the effective wr is shortened. data must be valid before the rising edge of wr . interrupt acknowledge cycle timing figure 23 displays an interrupt acknowle dge cycle timing. between the time intack goes low and the falling edge of rd , the internal and external iei/ieo daisy chains settle. if there is an interrupt pending in the scc and iei is high when rd falls, the acknowl- edge cycle is intended for the scc. in this case, the scc can be programmed to respond to rd low by placing its interrupt vector on d7-d0. it then sets the appropriate interrupt- under-service latch internally. if the external daisy chain is not used, ac para meter #38 is required to settle the interrupt priority daisy chain internal to the scc. if th e external daisy chain is used, you must fol- low the equation in table 6 on page 50 for calculating th e required daisy-chain settle time. figure 22. write cycle timing ad add a address valid data valid wr d7-d0 ce intack a/b , d/c
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 41 z80c30 timing the scc generates internal control signals from as and ds that are related to pclk. because pclk has no phase relationship with as and ds , the circuitry generating these internal control signals must provide time for metastable co nditions to disappear. this gives rise to a recovery time related to pclk . the recovery time applies only between bus transactions involving th e scc. the recovery time required for proper operation is speci- fied from the falling edge of ds in the first transaction in volving the scc to the falling edge of ds in the second tr ansaction involving the scc. the timings for z80c30 device is described below: ? read cycle timing ? write cycle timing ? interrupt acknowledge cycle timing read cycle timing figure 24 displays the read cycle timing. the address on ad7?ad0 and the state of cs0 and intack are latched by the rising edge of as . r/w must be high to indicate a read cycle. cs1 must also be high for the read cycl e to occur. the data bus drivers in the scc are then enabled while ds is low. figure 23. interrupt acknowledge cycle timing d7?d0 rd intack vector
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 42 write cycle timing figure 25 displays the write cycle timing. the address on ad7?ad0 and the state of cs0 and intack are latched by the rising edge of as . r/ w must be low to indicate a write cycle. cs1 must be high for the write cycle to occur ds low strobes the data into the scc. figure 24. read cycle timing intack ds as cs0 r/ w cs1 ad7?ad0 address data valid
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 43 interrupt acknowledge cycle timing figure 26 displays the interrupt acknowledge cycle timing. the address on ad7?ad0 and the state of cs0 and intack are latched by the rising edge of as . if intack is low, the address and cs0 are ignored. the state of the r/w and cs1 are also ignored for the duration of the interrupt acknowledge cycle. between the rising edge of as and the falling edge of ds , the internal and external iei/ieo daisy chains settle. if there is an interrupt pending in the scc, and iei is high when ds falls, the acknowledge cycle was intended for the scc. in this case, the scc is programmed to respond to rd low by plac- ing its interrupt vector on d7-d0 and internally setting the appropriate interrupt-under- service latch. figure 25. write cycle timing intack ds as cs0 r/w cs1 ad7?ad0 address data
ps011706-0511 functional descriptions cmos scc serial communications controller product specification 44 figure 26. interrupt acknowledge cycle timing ad7?ad0 ds (ignored) (ignored) vector as cs0 intack
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 45 electrical characteristics the electrical characteristics of the z80c30 an d the z85c30 devices are described in the following sections. absolute maximum ratings stresses greater than those listed in table 3 may cause permanent damage to the device this is a stress rating only. op eration of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the dc characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. all vo ltages are referenced to gnd. positive cur- rent flows into the referenced pin. see figure 27 and figure 28. ? +4.50 v ? v cc ? + 5.50 v ? gnd = 0 v ? t a (see ordering information ) table 3. absolute maximum ratings vcc supply voltage range ?0.3 v to +7.0 v voltages on all pins with resp ect to gnd ?3 v to vcc +0.3 v t a operating ambient temperature see ordering information storage temperature ?65 c to +150 c
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 46 39 figure 27. standard test load figure 28. open-drain test load +5 v 100 pf 250 ?a 2.1 k ? from output under test from output +5 v 50 pf 2.2 k ?
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 47 capacitance table 4 lists the input, output and bidirectional capacitance. miscellaneous the gate count is 6800. dc characteristics table 5 lists the dc characteristics for the z80c30 and z85c30 devices. table 4. capacitance symbol parameter min max unit test condition c in input capacitance 10 pf 1 unmeasured pins returned to ground 2 c out output capacitance 15 pf c i/o bidirectional capacitance 20 pf notes: 1. pf = 1 mhz, over specified temperature range. 2. unmeasured pins returned to ground. table 5. z80c30/z85c30 dc characteristics symbol parameter min ty p max unit condition v ih input high voltage 2.2 v cc +0.3 1 v v il input low voltage ?0.3 0.8 v v oh1 output high voltage 2.4 v i oh = ?1.6 ma v oh2 output high voltage v cc ? 0.8 v i oh = ?250 ? a v ol output low voltage 0.4 v i ol = +2.0 ma i il input leakage ? 10.0 ? a0.4 v in + 2.4 v i ol output leakage ? 10.0 ? a0.4 v out + 2.4 v i cc1 v cc supply current 2 7 12 (10 mhz) ma v cc = 5 v; v ih = 4.8 v il = 0 9 15 (16.384 mhz) ma crystal oscillator off i ccosc crystal osc current 3 4 ma current for each osc in addition to i cc1 notes: 1. v cc = sv t10% unless otherwise specifi ed, over specified temperature range. 2. typical i cc was measured with oscillator off. 3. no i cc (osc) max is specified due to dependency on external circuit and frequency of oscillation.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 48 ac characteristics figures 29 through 32 display read and write timing for the z85c30 device. figure 29. z85c30 read/write timing diagram pclk a/b , d/c intack ce rd d7?d0 read wr d7?d0 write w /req wait w /req request dtr /req request int 6 1 2 5 11 13 10 16 19 22 active valid 23 25 27 28 31 29 32 33 34 37 35 36 24 26 17 20 30 3 4 7 10 15 18 12 14 9 21
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 49 figure 30. z85c30 interrupt acknowledge timing diagram figure 31. z85c30 cycle timing diagram d7?d0 int pclk intack rd iei ieo 41 38 10 23 active valid 10 14 24 26 42 40 38 15 45 44 43 ce 49b 49b 49a pclk or wr
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 50 table 6 lists the read/write timing parameters for the z85c30 device. figure 32. z85c30 reset timing diagram table 6. z85c30 read/write timing no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max 1 twpci pclk low width 45 2000 40 2000 26 2000 2 twpch pclk high width 45 2000 40 2000 26 2000 3 tfpc pclk fall time 10 10 5 4 trpc pclk rise time 10 10 5 5 tcpc pclk cycle time 118 4000 100 4000 61 4000 6 tsa(wr) address to wr fall setup time 66 50 35 7 tha(wr) address to wr rise hold time 000 8 tsa(rd) address to rd fall setup time 66 50 35 9 tha(rd) address to rd rise hold time 000 notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. open-drain output, measured with open-drain test load. 3. parameter applies to enhanced request mode oniy (wr7? d4 = 1). 4. parameter is system-dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of tdpc(ieo) for the highest priority device in the dai sy chain. tsiei(rda) for the scc and tdiei(ieo) for each device separating them in the daisy chain. 5. parameter applies only between transacti ons involving the z85c30 sl1480, if wr/rd falling edge is synchro- nized to pclk falling edge, then trc = 3tcpc. 6. this specification is only applicable when valid access recovery time is less than 35 pclk. 48 rd wr 47 48
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 51 10 tsia(pc) intack to pclk rise setup time 20 20 15 11 tsiai(wr) 1 intack to wr fall setup time 140 120 70 12 thia(wr) intack to wr rise hold time 00 0 13 tsiai(rd) 1 intack to rd fall setup time 140 120 70 14 thia(rd) intack to rd rise hold time 00 0 15 thia(pc) intack to pclk rise hold time 38 30 15 16 tscei(wr) ce low to wr fall setup time 00 0 17 thce(wr) ce to wr rise hold time 00 0 18 tsceh(wr) ce high to wr fall setup time 58 50 30 19 tscei(rd) 1 ce low to rd fall setup time 000 20 thce(rd) 1 ce to rd rise hold time 000 21 tsceh(rd) 1 ce high to rd fall setup time 58 50 30 22 twrdi 1 rd low width 145 125 70 table 6. z85c30 read/write timing (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. open-drain output, measured with open-drain test load. 3. parameter applies to enhanced request mode oniy (wr7? d4 = 1). 4. parameter is system-dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of tdpc(ieo) for the highest priority device in the dai sy chain. tsiei(rda) for the scc and tdiei(ieo) for each device separating them in the daisy chain. 5. parameter applies only between transacti ons involving the z85c30 sl1480, if wr/rd falling edge is synchro- nized to pclk falling edge, then trc = 3tcpc. 6. this specification is only applicable when valid access recovery time is less than 35 pclk.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 52 23 tdrd(dra) rd fall to read data active delay 000 24 tdrdr(dr) rd rise to data not valid delay 000 25 tdrdi(dr) rd fall to read data valid delay 135 120 70 26 tdrd(drz) rd rise to read data float delay 38 35 30 27 tda(dr) addr to read data valid delay 210 160 100 28 twwri wr low width 145 125 75 29 tdwr(dw) wr fall to write data valid delay 35 35 20 30 thdw(wr) write data to wr rise hold time 00 0 31 tdwr(w) 2 wr fall to wait valid delay 168 100 50 32 tdrd(w) 2 rd fall to wait valid delay 168 100 50 33 tdwrf(req) wr fall to w /req not valid delay 168 120 70 34 tdrdf(req) 3 rd fall to w /req not valid delay 168 120 70 35a tdwrr(req) wr fall to dtr /req not valid 4tcpc 4tcpc 4tcpc table 6. z85c30 read/write timing (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. open-drain output, measured with open-drain test load. 3. parameter applies to enhanced request mode oniy (wr7? d4 = 1). 4. parameter is system-dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of tdpc(ieo) for the highest priority device in the dai sy chain. tsiei(rda) for the scc and tdiei(ieo) for each device separating them in the daisy chain. 5. parameter applies only between transacti ons involving the z85c30 sl1480, if wr/rd falling edge is synchro- nized to pclk falling edge, then trc = 3tcpc. 6. this specification is only applicable when valid access recovery time is less than 35 pclk.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 53 35b tdwrr(req) 3 wr fall to dtr /req not valid 168 100 70 36 tdrdrrreq) rd rise to dtr /req not valid delay na na na 37 tdpc(int) pclk fall to int valid delay 500 320 175 38 tdiai(rd) 4 intack to rd fall (ack) delay 145 90 50 39 twrda rd (acknowledge) width 145 125 75 40 tdrda(dr) rd fall (ack) to read data valid delay 135 120 70 41 tsiei(rda) iei to rd fall (ack) setup time 95 80 50 42 thiei(rda) iei to rd rise (ack) hold time 0 0 0 43 tdielrieo) iei to ieo delay time 95 80 45 44 tdpc(ieo) pclk rise to ieo delay 195 175 80 45 tdrda(int) 2 rd fall to int inactive delay 480 320 200 46 tdrdrwrq) rd rise to wr fall delay for no reset 15 15 10 47 tdwrq(rd) wr rise to rd fall delay for no reset 15 15 10 table 6. z85c30 read/write timing (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. open-drain output, measured with open-drain test load. 3. parameter applies to enhanced request mode oniy (wr7? d4 = 1). 4. parameter is system-dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of tdpc(ieo) for the highest priority device in the dai sy chain. tsiei(rda) for the scc and tdiei(ieo) for each device separating them in the daisy chain. 5. parameter applies only between transacti ons involving the z85c30 sl1480, if wr/rd falling edge is synchro- nized to pclk falling edge, then trc = 3tcpc. 6. this specification is only applicable when valid access recovery time is less than 35 pclk.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 54 48 twres wr and rd low for reset 145 100 75 49a trc e valid access recovery time 3.5tcpc 3.5tcpc 3.5tcpc 49b trci f rd or wr fall to pc fall setup time 0 0 0 table 6. z85c30 read/write timing (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. open-drain output, measured with open-drain test load. 3. parameter applies to enhanced request mode oniy (wr7? d4 = 1). 4. parameter is system-dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of tdpc(ieo) for the highest priority device in the dai sy chain. tsiei(rda) for the scc and tdiei(ieo) for each device separating them in the daisy chain. 5. parameter applies only between transacti ons involving the z85c30 sl1480, if wr/rd falling edge is synchro- nized to pclk falling edge, then trc = 3tcpc. 6. this specification is only applicable when valid access recovery time is less than 35 pclk.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 55 figure 33 displays a general timing diagram for the z85c30 device. figure 33. z85c30 general timing diagram sync input cts /trxc dcd cts /trxc rtxc cts /trxc output 22 22 22 22 20 18 19 16 17 14 15 1 2 6 7 4 5 8 9 3 12 11 13 txd rtxc transmit cts /trxc , sync external 10 rxd rtxc receive cts /trxc , w /req wait w /req request pclk
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 56 table 7 lists the general timing ch aracteristics for the z85c30 device. table 7. z85c30 general timing table no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max 1 tdpc(req) pclk to w/req valid 250 150 80 2 tdpc(w) pclk to wait inactive 350 250 180 3 tsrxc(pc) rxc to pclk setup time 1,2 n/a n/a n/a 4 tsrxd(rxcr) rxd to rxc setup time 1 0 0 0 5 thrxd(rxcr) rxd to /rxc hold time 1 150 125 50 6 tsrxd(rxcf) rxd to /rxc setup time 1,3 0 0 0 7 thrxd(rxcf) rxd to /rxc hold time 1,3 150 1 25 50 8 tssy(rxc) sync to rxc setup time 1 ?200 ?150 ?100 9 thsy(rxc) sync to rxc hold time 1 5tcpc 5tcpc 5tcpc 10 tstxc(pc) txc to pclk setup time 4,5 n/a n/a n/a 11 tdtxcf(txd) txc to txd delay 4 200 150 80 12 tdtxcr(txd) txc to txd delay 3,4 200 150 80 13 tdtxd(trx) txd to trxc delay 200 140 80 14a twrtxh rtxc high width 6 150 120 80 14b twrtxh(e) rtxc high width 7 50 40 15.6 15a twrtxi trxc low width 6 150 120 80 15b twrtxi(e) rtxc low width 7 50 40 15.6 16a tcrtx rtxc cycle time 6,8 488 400 244 16b tcrtx(e) rtxc cycle time 7 125 100 31.25 17 tcrtxx crystal osc. period 9 125 1000 100 1000 62 1000 18 twtrxh trxc high width 6 150 120 180 notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. synchronization of rxc to pclk is el iminated in divide by four operation. 3. parameter applies only to fm encoding/decoding. 4. txc is trxc or /rtxc, whichever is supplying the transmit clock. 5. external pclk to rtxc or txc synchronization require ment eliminated for pclk divide-by-four operation.trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc.tx and rx input clock slew rates should be kept to a maximum of 30 nsec . all parameters related to input clk edges must be referenced at the point at which the transiti on begins or ends, whichever is worst case. 6. parameter applies only for transmitter and receiver ; dpll and baud rate generator timing requirements are identical to case pclk requirements. 7. enhanced feature ? rtxc used as input to internal dpll only. 8. the maximum receive or transmit data rate is 1/4 pclk. 9. both rtxc and sync have 30 pf capacitors to ground connections.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 57 19 twtrxi trxc low width 6 150 120 80 20 tctrx trxc cycle time 6,8 488 400 244 21 twext dcd or cts pulse width 200 120 70 22 twsy sync pulse width 200 120 70 table 7. z85c30 general timing table (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. synchronization of rxc to pclk is el iminated in divide by four operation. 3. parameter applies only to fm encoding/decoding. 4. txc is trxc or /rtxc, whichever is supplying the transmit clock. 5. external pclk to rtxc or txc synchronization require ment eliminated for pclk divide-by-four operation.trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc.tx and rx input clock slew rates should be kept to a maximum of 30 nsec . all parameters related to input clk edges must be referenced at the point at which the transiti on begins or ends, whichever is worst case. 6. parameter applies only for transmitter and receiver ; dpll and baud rate generator timing requirements are identical to case pclk requirements. 7. enhanced feature ? rtxc used as input to internal dpll only. 8. the maximum receive or transmit data rate is 1/4 pclk. 9. both rtxc and sync have 30 pf capacitors to ground connections.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 58 figure 34 displays the system timing for the z85c30 device. figure 34. z85c30 system timing diagram 10 int sync input int cts , dcd dtr /req request wait w /req request w /req trxc , rtxc transmit int sync output wait w /req request w /req rtxc , trxc receive 9 8 7 6 6 4 3 1 2
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 59 table 8 lists the system timing char acteristics for the z85c30 device. table 9 provides the read/write timing characteristics for the z85c30 device. table 8. z85c30 system timing table no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max 1 tdrxc(req) rxc high to w /req valid 1,2 8 12 8 12 8 12 2 tdrxc(w) rxc high to wait inactive 1,2,3 8 14 8 14 8 14 3 tdrdxc(sy) rxc high to sync valid 1,2 4747470 4 tsrxc(int) rxc high to int valid 1,2,3 10 16 10 16 10 16 5 tdtxc(req) txc low to w /req valid 2,4 5 8 5 8 5 8 6 tdtxc(w) txc low to wait inactive 2,3,4 5 11 5 11 5 11 7 tdtxc(drq) txc low to dtr /req valid 3,4 4 7 4 7 4 7 8 tdtxc(int) txc low to int valid 2,3,4 6 10 6 10 6 10 9a tdsy(int) sync to int valid 2,3 2 6 2 6 2 6 9b tdsy(int) sync to int valid 2,3,5 2 3 2 3 2 3 10 tdext(int) dcd or cts to int valid 2,3 2 6 2 6 2 6 notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. units equal to tcpc. 3. open-drain output, measured with open-drain test load. 4. txc is trxc or rtxc whichever is supplying the transmit clock. 5. units equal to as. table 9. z85c30 read/write timing no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max 1 twpci pclk low width 45 2000 40 2000 26 2000 2 twpch pclk high width 45 2000 40 2000 26 2000 3 tfpc pclk fail time 10 10 5 4 trpc pclk rise time 10 10 5 5 tcpc pclk cycle time 118 4000 100 4000 61 4000 6 tsa(wr) address to wr fail setup time 66 50 35 7 tha(wr) address to wr rise hold time 0 0 0 8 tsa(rd) address to rd fall setup time 66 50 35
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 60 9 tha(rd) address to rd rise hold time 0 0 0 10 tsia(pc) intack to pclk rise setup time 20 20 15 table 9. z85c30 read/write timing (continued) no symbol parameter 8.5 mhz 10 mhz 16 mhz min max min max min max
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 61 figures 35 through 37 display the read/wr ite timing, interrupt acknowledge timing and reset timing, respectively, for the z80c30 device. figure 35. z80c30 read/write timing diagram wait w /req request pclk 42 40 41 43 44 44 27 int dtr /req request w /req 25 26 24 22 15 15 16 17 16 12 13 19 21 ad7?ad0 read ad7?ad0 write ds 12 write r /w write r /w read intack 7 8 9 cs1 cs0 7 4 4 14 6 10 10 18 20 23 2 as
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 62 figure 36. z80c30 interrupt acknowledge timing diagram figure 37. z80c30 reset timing diagram int ieo iei 36 35 34 32 31 22 33 20 30 19 29 8 7 ad7?ad0 ds intack as ds as 37 38 35
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 63 table 10 provides the read/write timi ng characteristics for the z80c30 device. table 10. z80c30 read/write timing 1 no symbol parameter 8 mhz 10 mhz min max min max 1 twas as low width 35 30 2 tdds(as) ds rise to as fall delay 2 15 10 3 tscso(as) cs0 to as rise setup time 2 0 0 4 thcso(as) cs0 to as rise hold time 2 30 20 5 tscs1(ds) cs1 to ds fall setup time 2 65 50 6 thcs1(ds) cs1 to ds rise hold time 2 30 20 7 tsia(as) intack to as rise setup time 10 10 8 thia(as) intack to as rise hold time 150 125 9 tsrwr(ds) r/w (read) to ds fall setup time 65 50 10 thrw(ds) r/w to ds rise hold time 0 0 11 tsrww(ds) r/w (write) to ds fall setup time 0 0 12 tdas(ds) as rise to ds fall delay 30 20 13 twdsi ds low width 150 125 14 trc valid access recovery time 3 4tcpc 4tcpc 15 tsa(as) address to as rise setup time 2 10 10 16 tha(as) address to as rise hold time 2 25 20 17 tsdw(ds) write data to ds fall setup time 15 10 18 thdw(ds) write data to ds rise hold time 0 0 19 tdds(da) ds fall to data active delay 0 0 20 tddsr(dr) ds rise to read data not valid delay 0 0 21 tddsf(dr) ds fall to read data valid delay 140 120 22 tdas(dr) as rise to read data valid delay 250 190 notes: 1. units in nanoseconds (ns) unless otherwise noted. 2. parameter does not apply to interrupt acknowledge transactions. 3. parameter applies only between transactions involving the scc. 4. float delay is defined as the time required for a ? 0.5 v change in the output with a maximum dc load and a min- imum ac load. 5. open-drain output, measured with open-drain test load. 6. parameter is system dependent. for any z-scc in the da isy chain. tdas(dsa) must be greater than the sum of tdas(ieo) for the highest priority device in the daisy ch ain tsiei(dsa) for the z-scc, and tdielf(ieo) for each device separating them in the daisy chain. 7. parameter applies only to a z-scc pulling int low at the beginning of the interrupt acknowledge transaction. 8. internal circuitry allows for the reset provided by the zb to be recognized as a reset by the z-scc. all timing ref- erences assume 20 v for a logic ?1? and 08 v for a logic ?0?.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 64 23 tdds(drz) ds rise to read data float delay 4 40 35 24 tda(dr) address requir ed valid to read data valid delay 260 210 25 tdds(w) ds fall to wait valid delay 5 170 160 26 tddsf(req) ds fall to w /req not valid delay 170 160 27 tddsr(req) ds fall to dtr /req not valid delay 4tcpc 4tcpc 28 tdas(int) as rise to int valid delay 5 500 500 29 tdas(dsa) as rise to ds fall (acknowledge) delay 6 250 225 30 twdsa ds (acknowledge) low width 150 125 31 tddsa(dr) ds fall (acknowledge) to read data valid delay 140 120 32 tsiei(dsa) iei to ds fall (acknowledge) setup time 80 80 33 thiei(dsa) iei to ds rise (acknowledge) hold time 0 0 34 tdiei(ieo) iei to ieo delay 90 90 35 tdas(ieo) as rise to ieo delay g 200 175 36 tddsa(int) ds fall (acknowledge) to int inactive delay 5 450 450 37 tdds(asq) ds rise to as fall delay for no reset 15 15 38 tdasq(ds) as rise to ds fall delay for no reset 20 15 39 twres as and ds coincident low for reset h 150 100 40 twpci pclk low width 50 1000 40 1000 table 10. z80c30 read/write timing 1 (continued) no symbol parameter 8 mhz 10 mhz min max min max notes: 1. units in nanoseconds (ns) unless otherwise noted. 2. parameter does not apply to interrupt acknowledge transactions. 3. parameter applies only between transactions involving the scc. 4. float delay is defined as the time required for a ? 0.5 v change in the output with a maximum dc load and a min- imum ac load. 5. open-drain output, measured with open-drain test load. 6. parameter is system dependent. for any z-scc in the da isy chain. tdas(dsa) must be greater than the sum of tdas(ieo) for the highest priority device in the daisy ch ain tsiei(dsa) for the z-scc, and tdielf(ieo) for each device separating them in the daisy chain. 7. parameter applies only to a z-scc pulling int low at the beginning of the interrupt acknowledge transaction. 8. internal circuitry allows for the reset provided by the zb to be recognized as a reset by the z-scc. all timing ref- erences assume 20 v for a logic ?1? and 08 v for a logic ?0?.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 65 41 twpch pclk high width 50 1000 40 1000 42 tcpc pclk cycle time 125 2000 100 2000 43 trpc pclk rise time 10 10 44 tfpc pclk fall time 10 10 table 10. z80c30 read/write timing 1 (continued) no symbol parameter 8 mhz 10 mhz min max min max notes: 1. units in nanoseconds (ns) unless otherwise noted. 2. parameter does not apply to interrupt acknowledge transactions. 3. parameter applies only between transactions involving the scc. 4. float delay is defined as the time required for a ? 0.5 v change in the output with a maximum dc load and a min- imum ac load. 5. open-drain output, measured with open-drain test load. 6. parameter is system dependent. for any z-scc in the da isy chain. tdas(dsa) must be greater than the sum of tdas(ieo) for the highest priority device in the daisy ch ain tsiei(dsa) for the z-scc, and tdielf(ieo) for each device separating them in the daisy chain. 7. parameter applies only to a z-scc pulling int low at the beginning of the interrupt acknowledge transaction. 8. internal circuitry allows for the reset provided by the zb to be recognized as a reset by the z-scc. all timing ref- erences assume 20 v for a logic ?1? and 08 v for a logic ?0?.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 66 figure 38 displays a general timing diagram fo r the z80c30 device, and table 11 lists its associated general tim ing characteristics. figure 38. z80c30 general timing diagram sync input 22 22 22 22 cts , dcd trxc rtxc trxc output trxc , rtxc transmit sync external rxd rtxc , trxc receive w /req wait w /req request pclk 20 19 18 16 17 14 15 13 8 11 10 9 4 5 6 3 7 1 2 12 txd
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 67 table 11. z80c30 general timing 1 no symbol parameter 8 mhz 10 mhz min max min max 1tdpc(req) pclk low to w/req valid 250 200 2tspc(w) pclk low to wait inactive 350 300 3 tsrxc(pc) rxc high to pclk high setup time 2,3 na na na na 4 tsrxd(rxcr) rxd to rxc high setup time 0 0 5 thrxd(rxcr) rxd to rxc high hold time 2 150 125 6 tsrxd(rxcf) rxd to rxc low setup time 2,4 0 0 7 thrxd(rxcf) rxd to rxc low hold time 2,4 150 125 8 tssy(rxc) sync to rxc high setup time 2 -200 -150 9 thsy(rxc) sync to rxc high hold time 2 5tcpc 5tcpc 10 tstxc(pc) txc low to pclk high setup time 3,5 na na 11 tdtxcf(txd) txc low to txd delay 5 190 150 12 tdtxcr(txd) txc high to txd delay 4,5 190 150 13 tdtxd(trx) txd to trxc delay 200 140 14 twrtxh rtxc high width 6 130 120 15 twrtxi trxc low width 6 130 120 16a tcrtx rtxc cycle time 6,7 472 400 16b txrx (dpll) dpll cycle time min 7,8 59 50 17 tcrtxx crystal osc. period 9 118 1000 100 1000 18 twtrxh trxc high width 6 130 120 19 twtrxi trxc low width 6 130 120 20 tctrx trxc cycle time 6,7 472 400 21 twext dcd or cts pulse width 200 120 22 twsy sync pulse width 200 120 notes: 1. units in nanoseconds (ns) otherwise noted. 2. rxc is rtxc or (trxc, whichever is supplying the receive clock. 3. synchronization of rxc to pclk is el iminated in divide by four operation. 4. parameter applies only to fm encoding/decoding. 5. txc is trxc or rtxc , whichever is supplyi ng the transmit clock. 6. parameter applies only for transmitter and receiver ; dpll and baud rate generator timing requirements are identical to case pclk requirements. 7. the maximum receive or transmit data rate is 1/4 pclk. 8. applies to dpll clock source oniy maximum data rate of 1/4 pclk still applies dpll clock should have a 50% duty cycle. 9. both rtxc and sync have 30 pf capacitors to ground connected to them.
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 68 figure 39 displays a system timing diagram fo r the z80c30 device, and table 12 lists its associated parameters. figure 39. z80c30 system timing diagram sync input cts , dcd trxc rtxc trxc output txd trxc , rtxc transmit sync external 22 22 21 21 20 18 19 17 18 14 15 11 10 12 rxd 10 rtxc , trxc receive w /req wait 9 8 4 5 3 w /req request pclk 6 7 2 1
ps011706-0511 electrical characteristics cmos scc serial communications controller product specification 69 table 12. z80c30 system timing no symbol parameter 8 mhz 10 mhz min max min max 1 tdrxc(req) rxc high to w /req valid 1,2 812812 2 tdrxc(w) rxc high to wait inactive 1,2,3 814814 3 tdrdxc(sy) rxc high to sync valid 1,2 4747 4 tdrxc(int) rxc high to int valid 1,2,3 812812 2 4 3 4 2 4 3 4 5 tdtxc(req) txc low to w /req valid e,2 5858 6 tdtxc(w) txc low to wait inactive 1,2,3 511511 7 tdtxc(drq) txc low to dtr /req valid 2,3 4747 8 tdtxc(int) txc low to int valid 1,2 4646 2 4 3 4 2 4 3 4 9a tdsy(int) sync to int valid 2,3 2626 9b tdsy(int) sync to int valid 2,3,4 2323 10 tdext(int) note 2,3,4 2323 notes: 1. rxc is rtxc or trxc whichever is supplying the receive clock. 2. units equal to tcpc. 3. open-drain output, measured with open-drain test load. 4. units equal to as . 5. txc is trxc or rtxc , whichever is supplyi ng the transmit clock.
ps011706-0511 packaging cmos scc serial communications controller product specification 70 packaging figure 40 displays the 40-pin dip package av ailable for the z80c30 and z85c30 devices. figure 40. 40-pin dip package diagram
ps011706-0511 packaging cmos scc serial communications controller product specification 71 figure 41 displays the 44-pin plastic le aded chip carriers (plcc) package diagram available for z80c30 and z85c30 devices. figure 41. 44-pin plcc package diagram
ps011706-0511 ordering information cmos scc serial communications controller product specification 72 ordering information table 13 provides ordering information for the z80c30 and the z85c30 devices. for complete details about zilog?s z80c30 and z85c30 devices, development tools and downloadable software, visit www.zilog.com . part number suffix designations zilog part numbers consist of a number of components, as indicated in the following example: part number z80c3016psg is a z80c30, 16 mhz, plcc, 0o c to +70o c, lead free table 13. z80c30/z85c30 ordering information 8 mhz 10 mhz 16 mhz z80c3008psg z80c3010psg z85c3016psg z80c3008vsg z80c3010vsg z85c3016vsg z85c3008psg/peg z85c3010psg/peg z85c3008vsg/veg z85c3010vsg/veg z 80c30 16 p s g environmental flow g = lead free temperature range s = 0o c to +70o c e = extended, ?40 c to +100 c package p = plastic dip v = plastic leaded chip carrier d = ceramic dip speed 8 = 8 mhz 10 = 10 mhz 16 = 16 mhz product number zilog prefix
ps011706-0511 customer support cmos scc serial communications controller product specification 73 customer support to share comments, get your technical questio ns answered, or report issues you may be experiencing with our products, please vi sit zilog?s technical support page at ? http://support.zilog.com . to learn more about this product, find additional documentation, or to discover other fac- ets about zilog product offerings, please visit the zilog knowledge base at http:// zilog.com/kb or consider participating in the zilog forum at http://zilog.com/forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .


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